Careers @ Cyrix

Engineering Opportunities

Chip-Set Designer

• Implementation of high-performance chip-sets in a semi-custom design environment. A thorough understanding of Verilog, logic synthesis, state machine design is required, as well as the ability to perform all levels of simulation, including full system-level simulation. The candidate will be responsible for behavioral design, logic synthesis, and simulation of high performance chip sets.
  Requires: 2+ years of directly related PC chip-set design experience (architect, chip set, or core logic design for desktop PC systems). Knowledge of advanced CPU architectures is helpful. Experience with transistor-level circuit design a plus. Minimum of BSEE, 3+ years experience in HDL design, logic synthesis, and state machine design. 3+ years designing ASICs required. Synopsys and Verilog experience mandatory. Experience with VLSI circuit design and VLSI physical layout a plus.
  Job Code: ROW-CSD

Chip-Set Design Manager

• Responsible for leading the implementation of high performance chip-sets in a semi-custom design environment. A thorough understanding of Verilog, logic synthesis, state machine design is required, as well as the ability to perform all levels of simulation, including full system-level simulation. The candidate will be responsible for behavioral design, logic synthesis, and simulation of high-performance chip sets.
  Requires: 3+ years directly related PC chip-set design experience (architect, chip set, or core logic design for desktop PC systems). Knowledge of advanced CPU architectures is helpful. Experience with transistor level circuit design a plus. Minimum of BSEE +5 years experience in HDL design, logic synthesis, and state machine design. 3+ years designing ASICs required. Synopsys and Verilog experience mandatory. Experience with VLSI circuit design and VLSI physical layout a plus.
  Job Code: ROW-CSM

Chip-Set Verification Engineer

• Define and drive the development of advanced verification systems to validate state-of-the-art PC architecture chip-sets. Work with the Chip Set and CPU architects to specify and architect the new x86-compatible PCs of the future.
  Requires: 4+ years of directly related PC chip-set design experience (architect, chip set, verification, or core logic design for desktop PC systems). Knowledge of advanced CPU architectures is helpful. Experience with transistor-level circuit design a plus. Job Code: ROW-CSVE

Circuit Designers

• Requires: World-class skills in VLSI design, plus BSEE/MSEE, along with 7 to 10 years experience. Must have strong knowledge of CMOS fabrication methods, leading edge circuit analysis/layout tools, circuit design guidelines and implementation review of state-of-the-art microprocessors.
  Job Code: ROW-SCD

Design Automation Engineers

• Senior engineers needed to define and implement design methods for state-of-the-art microprocessor design. The engineers will be involved in the development and integration of software tools for interconnect RC modeling and analysis, static timing analysis, behavioral/RTL/gate level modeling and simulation, formal verification, and datapath generators. The engineers will work closely with IC design engineers on definition, implementation, integration, and support of CAD tools.
  Requires: BSEE + 4 years experience, or MSEE + 2 years experience in VLSI design, software development (UNIX,C,C++); 1 year experience with layout CAD software algorithm development or 1 year experience with VLSI floorplanning.
  Job Code: ROW-DAE

Design Lead/Manager (Chipset Group)

• Design lead for Chipset Group. Will lead a team of engineers in a parallel design environment. Responsible for implementation of ASICs based on customer, marketing and engineering requirements. Will have architectural, design and managerial responsibilities. Should be willing and able to handle technical responsibility and personnel responsibility.
  Requires: BSEE with 5-8 years expr or MSEE with 4-6 years expr. Experience with ASIC design flow including synthesis, Verilog, or VHDL, static timing, test generation and design verification. Also, experience with 2-3 ASICs from design conception to production. Must know PC requirements; have experience in PC chipsets, modems or PCI peripherals.
  Job Code: ROW-DL

Design Verification (I) (Richardson, TX; Longmont, CO)

• Will perform design verification on advanced x86 processors and systems. Build and maintain behavioral models of processors and systems. Write and debug tests to verify the design is functionally correct as well as write tools.
  Requires: BSEE, BSCS or BSCE degree. Candidates must have good programming skills, familiarity with digital logic design and assembly language programming, and knowledge of computer architecture. Experience with perl, C++, Verilog and the x86 instruction set is preferred.
  Job Code: ROW-DV

Design Verification Engineer (Longmont, CO)

• Support the design of chipsets by implementing system level testcases, writing system behaviorals, and creating design verification environments. Will also include verification of design to spec, Verilog to gates, timing simulation. Some logic design required in addition to implementing tests to support HW bringup and debug.
  Requires: BSEE, BSCE or BSCS with 2-5 years expr. Experience with design verification environments in Verilog or VHDL. C++ coding experience, x86 architecture/programming experience and ASIC test and debug experience.
  Job Code: ROW-DVE

DSP/Modem Design Engineer (Longmont, CO)

• Design of Modem applications in x86 PC systems. Will work on design of HW/SW for modem and telephony applications and will work closely with the lead DSP designer.
  Requires: BSEE with 3-6 years related experience or MSEE with 2+ years related expr. Experience with Verilog or VHDL, static timing tools, test, and synthesis required. Experience with modem or telephone (speaker phone, caller-ID, echo-cancellation) required. Experience with production quality modem or telephony products.
  Job Code: ROW-DSP

DSP/Modem Designer/Architect (Senior) (Longmont, CO)

• Lead development of DSP/modem applications for x86 PC systems. This would include: modem, audio, speaker phone, echo cancellation, etc. HW and SW experience desired. Will lead the architecture and definition of designs in this area.
  Requires: Experience with DSP algorithm development and implementation for modems or telephony applications. BSEE with 5-8 years related experience or MSEE with 4-6 years related experience. Must have experience with Verilog or VHDL; industry standard DSP cores such as TI or OAK. Or experience implementing DSP designs using RISC processors. Knowledge of V.34bis and modem architectures: data pumps, error correction etc. Experience with RISC cores a plus, but not necessary.
  Job Code: ROW-DSP/ARC

DSP/VLSI Designer

• Circuit/Logic Design Engineer. Investigate the MMEU architecture and recommend implementation details for a high performance pipelined floating point unit. Implement the MultiMedia Extensions (MMX) of P55C for the FPU.
  Requires: Minimum BSEE/MSEE with 3+ years experience with strong emphasis in logic/circuit design/VLSI design. Design expertise in the area of Multimedia processors and algorithms required. Synopsys experience a must. Background in superscalar processor design and/or floating point systems a strong plus.
  Job Code: ROW-DSP/VLSI

Floating Point Architect

• Will implement a 'C' model for verifying the basic Add/Multiply/Divide/Sq-root operations. Extend this model to implement algorithms for transcendental and all other complex instructions. Develop/verify algorithms for all Transcendental functions including the logarithmic and exponential functions. Responsible for Ucode for all complex Instructions including divide and square-root. Will work closely with the designers of the Add/Multiply and Load/Store units. Specify boundary case tests for all Ucoded instructions. Perform error analysis of all floating-point operations.
  Requires:expertise in x86 Floating-point, numerical analysis and software skills. Minimum MSCS with emphasis on floating point or numerical analysis, or MS in applied mathematics required, PhD preferred. Strong interest and knowledge of floating point required. Knowledge of numerical methods of implementing transcendental functions required. Strong programming skills in C/C++.
  Job Code: ROW-FPA

Floating Point VLSI-Circuit Designer

• Help implement the Register File sections of a high performance pipelined floating point unit. Implement the physical and commit register files and the associated logic. Design expertise in the area of cams and associative memories required.
  Requires: Minimum BSEE/MSEE, with strong emphasis in circuit design/VLSI design, and 3+ years relevant experience. Background in superscalar processor design and/or floating point systems a strong plus.
  Job Code: ROW-FP/VLSI-CD

Floating Point VLSI-Logic Designer

• Help implement load/store/convert logic of a high performance pipelined floating point unit. Requires strong logic modeling and design skills.
  Requires: BSEE/MSEE with 3+ years experience. Experience with logic synthesis and static timing analysis a strong plus; logic modeling languages, such as verilog, are required. Good programming skills a plus; experience in superscalar design and floating point systems a strong plus.
  Job Code: ROW-FP/VLSI-LD

Floating Point VLSI-Logic Designer (A)

• Help Implement the execution control/scheduling sections of a high performance pipelined floating point unit. Implement the Add/Mul/Store/load Schedulers and the associated logic. Design expertise in the area of state machines/scheduling algorithms required.
  Requires: Min BSEE/MSEE, with strong emphasis in logic/circuit design/VLSI design, and 3+ years experience. Synopsys experience a must. Background in superscalar processor design and/or floating point systems a strong plus.
  Job Code: ROW-FP/VLSI-L(A)

IC Layout Designers

• Will be responsible for leading and coordinating of the layout for high speed multi-level metal processor designs. Will work closely with engineering to ensure that the finished product conforms to both electrical and physical guidelines necessary to produce the next generation circuits. Must be capable/willing to learn, use and incorporate the guidelines for state of the art layout tools. Must be able to grasp the whole picture of chip layout and pass that information on to other layout designers. Good communication skills and willingness to work with others a must.
  Requires: 5+ years of CMOS layout; 2+ years of chip lead experience; multi-level metal experience and high speed processors design experience required; and Cadence OPUS software; place and route exposure desired.
  Job Code: ROW-ICLD

Logic Design Engineer, Audio (Longmont, CO)

• Logic designer with experience in audio applications to include sound-blaster, wave table, MIDI, codecs, 3D sound, etc. Job will also include logic design in other areas as required. Will implement HW and work with SW group to provide complete solution. Design work may include all or some of: Verilog design entry, static timing analysis, architectural evaluation, performance analysis, and test.
  Requires: BSEE with 5-6 years expr or MSEE with 2-5 years expr. Experience with design of audio subsystems a plus. Experience with Verilog or VHDL, synthesis, static timing tools and test a plus.
  Job Code: ROW-LD/A

Logic Design Engineer, Chipset (Longmont, CO)

• Logic designer to support development of support chips for Cyrix processors. Responsible for design, test, and debug of 100K+ gate designs. Experience with HDL (Verilog or VHDL), synthesis, static timing analysis, test generation a plus.
  Requires: BSEE with 4-6 years related experience, or MSEE with 2-5 years related experience. Experience in PC related designs, audio, or PCI a plus.
  Job Code: ROW-LD/CS

Logic Design Engineer, Chipset (Senior) (Longmont, CO)

• Develop and architect for emerging PC Chipset designs including USB, Firewire, PCI, etc. Should be familiar with PC peripheral busses and there design. Knowledge of memory interfaces also desirable. Will be responsible for Cyrix based designs and support of emerging industry standard bus designs such as: USB, Firewire, PCI. Will be responsible for working with microprocessor group to provide HIGH bandwidth systems.
  Requires: BSEE with 4-6 years expr or MSEE with 3-5 years. Must have design level knowledge of USB and PCI. Design of a USB interface a plus. Experience with Verilog or VHDL, synthesis, static timing tools and test a plus.
  Job Code: ROW-LD/CS-SR

Logic Design Engineer, Network Connectivity (Longmont, CO)

• Support of network interface hardware for x86 PC systems. Must be familiar with Ethernet 10BaseT and 100BaseT designs or modem V.34bis designs. Knowledge of these designs in a PCI environment is desirable. Design will include some or all of the following: architectural evaluation and definition, performance analysis, HDL logic design, synthesis, static timing analysis, and test.
  Requires: BSEE with 3-6 years related experience or MSEE with 2-5 years related experience. Must have experience with Verilog or VHDL, logic synthesis, static timing tools, ASIC designs.
  Job Code: ROW-LD/NC

Logic Designers

• Requires: BSEE/CS with strong software/architecture/logic design skills. Experience with behavioral modeling in Verilog (or similar language), logic synthesis (Synopsys), static timing analyzers and emulation techniques a plus. x86 experience preferred.
  Job Code: ROW-LD

Software Engineer (SE) (Longmont, CO)

• Responsible for adding power management to Cyrix-based systems and helping port the Cyrix chipset BIOS code to various core BIOSes. Knowledge of x86 assembly, C and PC BIOS required. Knowledge of APM and SMI based power management and Windows 95 drivers a plus.
  Job Code: ROW-SE

Software Engineer (SWE) (Longmont, CO)

• Will be responsible for development of multimedia software for Windows '95/NT including audio wavetable synthesis, MPEG video and 3D graphics; architecture and development of PC notebook and desktop reference platforms. Will participate directly in advanced microprocessor and chipset hardware design for next generation personal computers.
  Requires: BSCS, BSEE or BSCE with a 3.0+ GPA
  Job Code: ROW-SWE

System Architect

• Define and drive the development of advanced, high-performance x86 PC systems. Participate in the development of PC chip-sets to realize the fastest PCs in the industry. Work directly with CPU developers and architects to make trade-offs between the CPU and system logic to optimize system performance and features. Analyze system design alternatives, prove architectural concepts, and define new product features.
  Requires: The ideal candidate with have 5+ years designing PC systems, specifying feature sets, writing system specs, working with chip set providers, and leading the implementation of system development. The candidate must also understand PC AT compatibility, board and electrical timing issues, and a deep mastery of the PC industry infrastructure specifying and qualifying peripheral components. Minimum of BSEE + 5 years experience in HDL design, logic synthesis, and state machine design. 3+ years designing ASICs required. Experience with VLSI circuit design and VLSI physical layout a plus.
  Job Code: ROW-SA

Verification Engineers

• Will design verification strategies for CISC microprocessor designs; includes assembly language programming, high level language programming, and development of tool concepts; x86 programming a plus.
  Requires: BSEE plus 3 years experience in verification or design of microprocessors.
  Job Code: ROW-VE

VLSI/Circuit Design (Longmont, CO)

• Support design effort of next generation microprocessors and supporting chipsets for notebook or low power systems. This would include logic synthesis, timing, circuit design and/or test.
  Requires: MSEE or MSCE. Emphasis in computer architecture or circuit design (VLSI). Experience with Verilog, Synopsys or IBM PCs a plus.
  Job Code: ROW-VCD

VLSI Design Engineers

• Will implement complex high speed VLSI circuits utilizing state of the art CMOS processing technology. Challenges include high speed synchronous and asynchronous design with power management considerations. Will be part of a complete product development team responsible for seeing a design from conception to completion.
  Requires: BSEE plus 3 to 5 years experience, or MSEE plus 2 years experience in CMOS logic and circuit design.
  Job Code: ROW-VLSI

VLSI Foundry/Design Engineers

• Requires: BSEE/MSEE plus 4 years experience in CMOS transistor-level circuit design, simulation, custom CMOS layout, design rules checking software and strong knowledge of sub-micron CMOS fabrication technologies. Process development and state-of-the-art SRAM design experience a plus.
  Job Code: ROW-FDE