The Cyrix MediaGX System establishes a new class of low-cost, high-performance desktop and notebook PC computers. This system eliminates the traditional audio and video cards, and all AT motherboard components of a PC.
The MediaGX System consists of two chips--the MediaGX processor and the MediaGX Cx5510 companion chip.
The audio and graphics functions of the two chips operate under the control of the Virtual System Architecture™ (VSA) design. This design eliminates system conflicts and end-user configuration problems.
The MediaGX processor is a 64-bit data bus, x86-compatible processor with a proven core. The CPU directly interfaces to a PCI bus and DRAM memory. High quality SVGA is provided by an advanced graphics accelerator on the MediaGX processor. The graphics frame buffer is stored in main memory without the performance degradation associated with traditional Unified Memory Architecture (UMA) system designs due to Cyrix's new Display Compression Technology (DCT).
The companion chip, the MediaGX Cx5510, represents a new generation of integrated, single-chip controllers for Cyrix's line of MediaGX-compatible 64-bit processors. The Cx5510 bridges the MediaGX processor over the PCI bus to the ISA bus, performs traditional chip-set functions, and supports a sound interface compatible with industry-standard sound cards.
MediaGX Processor Feature Summary
64-Bit x86 Processor
Power Management
PCI Controller
Additional Features
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VSA Virtual VGA
Memory Subsystem
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The MediaGX processor not only executes x86 instructions using a proven Cyrix CPU core, it also acts as a virtual video card. This chip provides a high-quality video port that connects directly to a flat panel or to an external RAMDAC chip for CRT display. The processor also provides a 64-bit wide DRAM interface and video compression which allows video and main memory sharing without memory performance degradation.
The MediaGX processor core operates from a 3.3 or 3.6 volt power supply, resulting in low power consumption at all clock frequencies. Where additional power savings are required (especially in portable applications), designers can make use of suspend mode, stop clock capability, and System Management Mode (SMM).
Other features include:
The MediaGX processor is made up of eight major functional blocks, as shown below:
In general, data and code from DRAM or the PCI port travels over the X and C internal bus lines to the L1 cache where it is stored. Code instructions are fetched from the DRAM port or L1 cache by the execution core and floating point unit for processing.
Video data is processed by the graphics pipeline and video display controller. Output from the video display controller is sent to a CRT monitor (via a RAMDAC chip) or directly to a flat-panel monitor.
The PCI bus controller is used to control the PCI bus--there is no external CPU bus. The MediaGX Cx5510 performs functions such as interfacing to the IDE and I/O ports and the ISA bus.
The Execution Core fetches, decodes and executes integer x86 code instructions. The decoupled Load/Store unit allows multiple memory accesses to be processed in a single clock cycle. Other features include single-cycle execution, single-cycle instruction decode, 16-KByte Write-Back cache, and clocks rates up to 133 MHz. This high performance is made possible by the use of advanced process technologies and execution core design that has many pipelined stages (superpipelining).
There are six pipeline stages:
Write-Back allows data to be written to the cache and not immediately to main memory.
Often a software execution path loops through a set of instructions. The branch instruction at the bottom of the loop returns processing to the top of the loop except after the last loop iteration. The Branch Target Buffer (BTB) takes advantage of this phenomena and predicts correct branching more than 80% of the time.
The Floating Point Unit (FPU) allows floating point instructions to execute in parallel with integer instructions and features a 64-bit data interface. The FPU incorporates a four-deep instruction queue and a four-deep store queue to facilitate parallel execution.
The 16-KByte Unified Write-Back cache is a data/instruction cache and is configured as four-way set associative. This L1 cache stores up to 16-KBytes of code and data in 1024 cache lines. The cache features a scratch-pad memory that allows selected cache lines to be used for the MediaGX VSA and graphics software. Scratch-pad memory lines, in some cases, greatly speed up multi-media instruction processing.
The Internal Bus Controller provides a bridge between the C bus and the X bus. The bus controller provides configuration control for as many as 20 different regions in system memory with separate controls for read access, write access, cacheability and PCI bus access.
The PCI Controller is a full-function PCI interface module that supports cache line bursting, pacing of data during both read and write operations, permits up to three PCI masters and uses three types of arbitration.
The Graphics Pipeline is a full feature GUI accelerator that includes a complete bitBLT/rendering engine and support for all three-operand boolean raster operations. The graphics pipeline, controlled by a set of highly optimized Microsoft Windows 95 and NT drivers, provides outstanding GUI performance. The drivers and graphics pipeline are closely coupled in unique ways and have the capability to perform high-speed block transfers between virtual memory and the frame buffer.
The Display Controller interfaces the MediaGX processor to display devices. It provides direct interfaces to converts host data to TFT (Thin Film Transistor) flat panel displays and to RAMDAC (Random Access Memory Digital to Analog Converter) for driving CRTs.
The display controller retrieves image data from the frame buffer, inserts cursor and icon overlays into the pixel stream, generates display timing, and formats the pixel data for output to a variety of display devices.
A unique combination of hardware and software in the MediaGX provides
compatibility with VGA and VESA graphic standards. The graphics pipeline
and display controller are hardware assisted to support many VGA and VESA
data operations, but all the of the VGA registers and controls are virtualized
through Cyrix's Virtual System Architecture (VSA)
software.
VSA technology allows hardware to be replaced by software without sacrificing compatibility. Hardware to be virtualized is replaced with simple memory and I/O trapping hardware. When an application or non-Windows operating system attempts to access a VGA register or memory range, the MediaGX processor detects the access attempt and internally takes a System Management Interrupt (SMI) and enters into a highly-optimized System Management Mode (SMM).
When the MediaGX goes into SMM, it saves the processor state and invokes a VSA handler that determines the cause of the SMI. The VSA handler then calls a VSA graphics driver to process the graphics access. The handler and VSA driver run in a special enhanced SMM mode making operations completely transparent to the application and operating system.
While VSA technology provides full compatibility for all VGA and VESA modes and registers, the VSA graphic drivers take full advantage of the graphics pipeline boosting VGA performance in the MediaGX.
The MediaGX also uses VSA software to provide industry-standard sound card compatibility.
MediaGX Cx5510 Feature Summary
VSA Audio Controller
PCI to ISA Bridge
Additional Features
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AT Compatibility
Power Management
Bus Mastering IDE Controllers
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The MediaGX Cx5510 represents a new generation of integrated, single-chip controllers for Cyrix's MediaGX line of x86-compatible 64-bit processors. The Cx5510 is a bridge to the ISA bus, performs traditional chip-set functions and supports a full-featured, compatible sound interface.
The Cx5510 provides a PCI version 2.1 compatible interface operating up to 40 MHz. The Cx5510 contains a PCI to ISA bridge.
For AT compatibility, the Cx5510 emulates two 8237 DMA controllers, an 8254 interval timer, and decode logic for AT register space. The Cx5510, in conjunction with the MediaGX processor and the VSA design, enables audio functions compatible with industry standards. The chip also provides a MIDI audio port and a two-channel (four-device) Bus Mastering IDE controller.
Full-function power management allows for notebook as well as desktop designs.
The Cx5510 provides a PCI Bus interface that acts as both a slave for PCI cycles initiated by the CPU or their PCI master devices, or as a master for DMA and ISA master transfer cycles. The Cx5510 generates address and data parity and performs parity checking It does not include the PCI bus arbiter. The arbiter is located in the MediaGX processor.
The Cx5510 contains configuration registers that are accessed through the PCI interface.
The Cx5510 provides an ISA bus interface for subtractive-decoded memory and I/O cycles on the PCI bus. The Cx5510 supports ISA Bus Masters through the DMA controller. The Cx5510 supports the standard ISA refresh function.
The Cx5510 integrates advanced power management features including idle timers for common system peripherals, address trap registers for programmable address ranges (for I/O or memory accesses), three programmable general purpose external inputs, clock throttling with automatic speedup for the CPU clock, software CPU stop clock, zero-volt suspend/resume with peripheral shadow registers, and a dedicated series bus to and from the MediaGx microprocessor providing CPU power management status. The Cx5510 can virtually power the MediaGx processor off during a 3-volt suspend.
Cyrix Corporation (Cyrix) has invested substantial resources in filing/acquiring patents from the U.S. Patent and Trademark Office and similar governing bodies worldwide covering the use of computer related products. Pending or issued patents may apply to processes, systems, methods, software and/or circuits referenced in this manual.
Cyrix Corporation
P.O. Box 850118
Richardson, TX 75085-0118
Tel: (800) 462-9749
Tel: (972) 968-8388
94334-00 February 1997 (C) Cyrix Corporation. Cyrix is a registered trademark and MediaGX and Virtual System Architecture are trademarks of Cyrix Corporation. All other brand or product names are trademarks or registered trademarks of their respective holders.